The following HSPICE & IBIS model information is provided as a point of information to the User:

1]]  "socket_adapter_0.5mm.cir" This is the HSPICE model. It's is a 20-pole rational polynomial description of the device parasitics.  This is implemented as a subcircuit call with 8 nodes -- read "wires" -- numbered 1 through 8.  The header contains the mapping information of each node in terms of signals S1+ through S2- and whether it is the male or female terminal end.

2]]  "socket_adapter_0.5mm_ibis.txt" This file contains the header information which enables an IBIS-ICM version 1.1 compatible simulator to interpret the s-parameter matrix.  The header contains the mapping information of each port in the s-parameter matrix in terms of signals S1+ through S2-, and whether the port looks into the male or female terminal end.

3]]  "socket_adapter_0.5mm.s8p" This file contains the s-parameter matrix in the Touchstone, (raw data), format. This file may be imported into either HSPICE or IBIS model solvers.

NOTE:  The latest IBIS interconnect standard (IBIS-ICM version 1.1, ratified in July of 2005) implemented multi-port s-parameter matrices for modeling purposes.  This method provides a more efficient translation to the IBIS model and negates the previous requirement to generate RLGC matrices. HSPICE has also implemented rational-polynomial circuit descriptions for interconnect modeling purposes.  Most current EM Solvers can take advantage of this recent improvement to model translations and generate the HSPICE file in a more efficient manner.